1. Field of the Invention
The present invention relates to the manufacture of semiconductor devices. More particularly, the present invention is directed to a novel method for forming contact plugs and simultaneously planarizing a substrate surface in integrated circuits.
2. Description of the Related Art
As integrated circuit devices become more complex, greater numbers of interconnect levels are required to connect the various sections of the device. Generally contact vias are formed between interconnect levels to connect one level to another. When multiple layers of interconnects are used in this manner, however, difficulties arise in forming upper interconnect levels and contact vias due to the uneven topographical features caused by the lower interconnect levels. Thus, the topography of interconnect levels affects the ease of manufacturing of the integrated circuit device.
The uneven topographical features of multiple interconnect levels are caused by forming the various interconnect layers above each other, resulting in the creation of hills and valleys on the surface of the device. Those skilled in the art will recognize it is difficult to get upper interconnect layers to maintain constant cross-sections when crossing over uneven topography. This leads to portions of the interconnect line having a higher current density, leading to electromigration problems and related device failure mechanisms. These step coverage problems can result in voids and other defects in the interconnect signal lines themselves, and in the contact vias formed between interconnect lines.
Examples of other defects in the interconnect signal lines are open-circuits or short-circuits between layers resulting from the uneven topography caused by the various interconnect layers in a multi-layer structure.
Another example of defects in the interconnect signal lines is the use of a conventional method for forming contact plugs in which a very thick layer of insulating material must be grown or deposited on an underlying region (or a semiconductor substrate) to form contact plugs. According to this conventional method, the contact plugs are formed by using a chemical mechanical polishing (CMP) process which is performed immediately after a conductive layer is deposited filling up contact holes or vias formed through the very thick insulating layer. The insulating layer must be made very thick to accommodate the CMP process for forming the contact plugs. When contact holes or vias are formed through the very thick insulating layer, the aspect ratio of the holes or vias is increased. This leads to two other defects. First, voids may be generated when a conductive layer is deposited on the very thick insulating layer filling up the contact holes or vias. Second, the CMP processing time is increased since the insulating layer is very thick.
Therefore, it would be desirable to provide a method for forming contact vias which are free of voids and other defects, and which result in a more planar topography. It is also desirable that such a method not significantly increase the complexity of the manufacturing process.